3D Volumetric Display Design Challenges

31st Norchip Conference 2013
Krišs Osmanis, Gatis Valters, Ilmārs Osmanis

This paper presents and analyses several challenges of 3D volumetric display design process. Designs with video transfer and processing requires huge amounts of data bandwidth, thus most of the work is done with high-speed programmable logic chips. Introduction to volumetric technology is given and main design blocks and steps are explained. Results show that it is possible to implement all main building blocks within single Virtex-6 FPGA with higher performance and better spatial parameters, in comparison of previous generation volumetric display.

Keywords
Volumetric Display, Virtex-6, FPGA, 3D, DisplayPort, DLP, DMD, DDR3
DOI
10.1109/NORCHIP.2013.6702001
Hyperlink
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6702001

Osmanis, K., Valters, G., Osmanis, I. 3D Volumetric Display Design Challenges. In: 31st Norchip Conference, Lithuania, Vilnius, 11-12 November, 2013. Vilnius: 2013, pp.1-4. Available from: doi:10.1109/NORCHIP.2013.6702001

Publication language
English (en)