FPGA Implementation and Study of Synchronization of Modified Chua’s Circuit-Based Chaotic Oscillator for High-Speed Secure Communications

2020 IEEE 8th Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE 2020) 2021
Filips Čapligins, Anna Litviņenko, Artūrs Āboltiņš, Deniss Kolosovs

This paper presents an implementation of modified Chua’s circuit-based chaos generator in a fieldprogrammable gate array (FPGA) and explores the synchronization of such generators for use in secure communication systems. The chaos generator design employs a fixed-point numeric format and the Forward Euler differential equation numerical solution method. The implementation of chaotic generator on Intel Cyclone V FPGA demonstrates the stable generation of sampled chaotic signal with up to 76 MHz clock frequency. The correctness of the realization is verified using a comparative analysis of the Simulink functional model and FPGA implementation.

Keywords
chaos generator, chaotic synchronization, field programmable gate arrays, direct digital synthesis
DOI
10.1109/AIEEE51419.2021.9435783
Hyperlink
https://ieeexplore.ieee.org/document/9435783

Čapligins, F., Litviņenko, A., Āboltiņš, A., Kolosovs, D. FPGA Implementation and Study of Synchronization of Modified Chua’s Circuit-Based Chaotic Oscillator for High-Speed Secure Communications. In: 2020 IEEE 8th Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE 2020), Lithuania, Vilnius, 22-24 April, 2021. Piscataway: IEEE, 2021, pp.119-124. ISBN 978-1-6654-3087-6. e-ISBN 978-1-6654-2538-4. e-ISSN 2689-7342. Available from: doi:10.1109/AIEEE51419.2021.9435783

Publication language
English (en)