Simplified Implementation of Compressed Sensing Reconstruction Algorithm in FPGA

2021 IEEE Microwave Theory and Techniques in Wireless Communications (MTTW 2021) 2021
Sandis Migla, Artūrs Āboltiņš, Mihails Pudžs, Dmitrijs Pikuļins, Juris Grizāns

This paper is devoted to the field-programmable gate array (FPGA) implementation of least-squares (LS)-based reconstruction method of one-dimensional signals recorded using compressed sensing (CS) approach. The main novelty of the proposed algorithm is simplicity and suitability for implementation in low-end FPGAs, such as Intel Cyclone®V. The paper focuses on solving problems when dealing with FPGA implementation of compressed sensing signal reconstruction. In order to make the reconstruction process simpler, in the theoretical part, the authors propose a simplified method for sparse spectrum recovery based on the LS. Some results from the practical implementation of the proposed algorithm into the Modelsim® FPGA simulator are reported.

Keywords
compressed sensing, signal processing, reconstruction algorithms, parallel processing, hardware, computing
DOI
10.1109/MTTW53539.2021.9607190
Hyperlink
https://ieeexplore.ieee.org/document/9607190

Migla, S., Āboltiņš, A., Pudžs, M., Pikuļins, D., Grizāns, J. Simplified Implementation of Compressed Sensing Reconstruction Algorithm in FPGA. In: 2021 IEEE Microwave Theory and Techniques in Wireless Communications (MTTW 2021), Latvia, Rīga, 7-8 October, 2021. Piscataway: IEEE, 2021, pp.12-17. ISBN 978-1-6654-2470-7. e-ISBN 978-1-6654-2469-1. Available from: doi:10.1109/MTTW53539.2021.9607190

Publication language
English (en)