An Asynchronous FIR Filter Architecture Coupled to a Level-Crossing ADC

Proceedings of the 9th International Conference on Sampling Theory and Applications (SampTA'11) 2011
Taha Beyrouthy, Laurent Fesquet, Rolands Šāvelis, Modris Greitāns, Rolland Robin

This paper presents the architecture of an asynchronous digital signal processing chain, working with non-uniformly sampled data in time. We focus on a Finite Impulse Response filter (FIR) applied to this non-uniform sampled signal obtained from an asynchronous analog to digital converter (A-ADC). The main advantage of combining the asynchronous design with the non-uniform sampling is the drastic reduction of the power consumption, thanks to the reduction of the computational load.

Atslēgas vārdi
Asynchronous logic, non-uniform sampling, FIR filter, FPGA
Hipersaite
http://sampta2011.ntu.edu.sg/SampTA2011Proceedings/papers/Fr2S12.2-P0190.pdf

Beyrouthy, T., Fesquet, L., Šāvelis, R., Greitāns, M., Robin, R. An Asynchronous FIR Filter Architecture Coupled to a Level-Crossing ADC. No: Proceedings of the 9th International Conference on Sampling Theory and Applications (SampTA'11), Singapūra, Singapore, 2.-6. maijs, 2011. Singapore: 2011, 1.-4.lpp.

Publikācijas valoda
English (en)