LUT-Oriented Asynchronous Logic Design Based on Resubstitution
2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS 2019) 2019
Igor Lemberski, Artjoms Supoņenkovs, Marina Uhanova

The method of asynchronous logic synthesis targeting area ((number of Look-Up-Tables -LUTs) minimization is proposed. Initially, a single-rail multi-level network is created using ABC synthesis system script. The improvement is done using the resubstitution. For the network compact representation and optimization, an extended PLA table is proposed. The resubstitution is formulated and solved as a covering task: the output of the node which input has been selected for the resubstitution is split into the set of dichotomies. The selected input is removed and the minimal number of inputs are sought to cover the dichotomies. Two-step procedure is proposed: 1) the resubstitution for a network produced by ABC is done; 2) the obtained network is transformed into dual-rail one and the resubstitution is done further. In each step, nodes with zero fan-outs are removed. The procedure guarantees indicating logic. The experiments show, that the result is more that 20% better w.r.t. number of nodes.


Atslēgas vārdi
logic synthesis, asynchronous logic, dual-rail function, look-up-table-LUT, resubstitution
DOI
10.1109/DTIS.2019.8734973
Hipersaite
https://ieeexplore.ieee.org/document/8734973

Lemberski, I., Supoņenkovs, A., Uhanova, M. LUT-Oriented Asynchronous Logic Design Based on Resubstitution. No: 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS 2019), Grieķija, Mykonos, 16.-18. aprīlis, 2019. Piscataway: IEEE, 2019, 1.-4.lpp. ISBN 978-1-7281-3425-3. e-ISBN 978-1-7281-3424-6. Pieejams: doi:10.1109/DTIS.2019.8734973

Publikācijas valoda
English (en)
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