Noise Performance Study of FPGA-based and Analog Chaos Oscillator Synchronization

2025 IEEE 12th Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2025 - Proceedings 2025
Ruslans Babajans, Deniss Kolosovs, Darja Čirjuļina, Sergejs Tjukovs, Nikolajs Bogdanovs, Dmitrijs Pikuļins

This article is devoted to studying the synchronization noise immunity of chaos oscillators implemented as analog circuits as well as the chaos oscillators implemented in the field-programmable gate array (FPGA) that exhibit similar behavior to their analog counterparts. The increasing use of analog and FPGA-based chaos oscillators for secure communication applications such as security improvement and information carriers lead to the idea of utilizing both oscillators in designing a chaos-based data transmission system. The hybrid analog-discrete implementation of chaos allows for more complex modulation schemes for wireless sensor networks. The core of such an approach is the possibility of synchronizing analog chaos with its discrete counterpart implemented on the FPGA. As data transmission is done in the wireless channel, the noise immunity of such synchronization is crucial to investigate, which is the focus of this work. © 2025 IEEE.

Atslēgas vārdi
chaotic oscillator; chaotic synchronization; nonlinear dynamics; secure communication
DOI
10.1109/AIEEE66149.2025.11050878
Hipersaite
https://ieeexplore.ieee.org/document/11050878

Babajans, R., Kolosovs, D., Čirjuļina, D., Tjukovs, S., Bogdanovs, N., Pikuļins, D. Noise Performance Study of FPGA-based and Analog Chaos Oscillator Synchronization. No: 2025 IEEE 12th Workshop on Advances in Information, Electronic and Electrical Engineering, AIEEE 2025 - Proceedings, Lietuva, Vilnius, 15.-17. maijs, 2025. Piscataway: Institute of Electrical and Electronics Engineers Inc., 2025, 1.-5.lpp. ISBN 978-166549688-9. Pieejams: doi:10.1109/AIEEE66149.2025.11050878

Publikācijas valoda
English (en)